![]() In current design methodologies, timing and cross-talk are analyzed at various process and temperature corners, also assuming a homogeneous temperature distribution across the chip for each corner case. As temperature variation has an impact on the slew rates of signals, it also has an impact on the cross-talk noise between signal lines. This affects the setup and hold time margins of circuits. Additionally, interconnect delay and slew also increase with rising temperature due to increased metal resistivity. With rising temperature, transistor drive strengths decrease due to carrier mobility degradation, leading to slower slew rates and gate delays. As a result, current thermal design methodologies fail to predict the correct total power dissipation and the maximum temperatures of the system. Thermal hot-spots, however, contribute significantly to the leakage power and the heat dissipation in the system. However, current design analysis methodologies typically assume an average system temperature based on estimates of the chip power dissipation and the thermal dissipation of the chip/package system, and do not consider the dependency between local temperature and leakage power, or model thermal hot-spots in the design. Therefore, power dissipation and temperature distribution are interdependent, and have to be considered simultaneously in order to achieve an accurate prediction of both the power consumption and the temperature distribution on the chip. At 45nm process node, leakage power increases quadratically with temperature, nearing dynamic power consumption at higher temperature.īut in addition, as leakage current increases with local temperature, local heat generation increases as a result. At 90nm process node, leakage power increases more than linearly with temperature.Ģ. ![]() The key design parameters affected by heat production and dissipation characteristics, and the resulting temperature variations across the chip, are:ġ. As a result, accurate thermal analysis is an essential part of the design process for modern SoC designs in today's technologies. Furthermore, local temperature distributions have an impact on the performance and reliability of integrated circuits. Local temperature hotspots, with higher- than- average temperatures, contribute over-proportionally to the total power dissipation of the system. Therefore, predicting the leakage power, and thus the total system power, requires detailed and accurate knowledge of the temperature distribution. As the dependency between leakage power and temperature is highly non-linear, knowing the average temperature of a system is not sufficient. In these systems, 30% or more of the total power dissipation can be caused by gate leakage, and leakage current is a strong function of local temperature. These low power design methodologies create their own thermal challenges, as they may generate “hot” and “cool” regions on the chip.Īt 90nm process node and below, an additional design constraint, such as leakage power, arises from thermal integrity considerations. SoC designers address this problem with one or more low-power design methodologies, such as switching off parts of the design when not in use. This creates severe challenges for the thermal design of packages and chips. As the complexity of chips scales according to Moore's Law, the power density, as well as the total power dissipation of chips, is still increasing. With the increasing complexity and power dissipation of modern electronic designs, controlling peak temperature and predicting the temperature profile on the chip early in the process is becoming critical for insuring system reliability.
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